Verification
A processor is only worth what its tests can show. Each row below is a check that runs in continuous integration on every change, and each one can fail.
| What | How much | Against |
|---|---|---|
| Official RISC-V instruction tests (rv32ui) | 40 of 42, both cores | The golden model. fence_i and ma_data are excluded: they need features this core does not have. |
| Hand-written programs | 5, both cores | The golden model for results; the timing model for pipeline cycles. |
| Random programs | 260, both forwarding modes | The golden model for results; the timing model for pipeline cycles. |
| Fault cases | 13 | The golden model: illegal instructions, bad accesses, misaligned jumps. |
| Mutation checks | 7 on the pipeline (Phase 3), 11 on hazards (Phase 4) | Each check must fail on a deliberately broken core. A check that passes on a broken core is itself a bug. |
| WASM module | 534 checks | Golden fixtures, on both cores, with forwarding on and off. |
| Web app | 67 unit tests and 9 browser tests | The assembler against GNU's bytes, and the presets on the WASM core. |
| Size budget | About 77 KB gzipped | The build fails above 400 KB. |
What "cycle-exact" means
The pipeline's cycle count is checked against an independent timing model written in Python
(sim/golden/pipemodel.py). The RTL and the model are two separate implementations of the same
timing rules, so agreement between them is evidence about both.
What is not verified yet
- Clock speed. Cycles are measured; time to finish needs the FPGA synthesis numbers, which are still to come.
- The two excluded riscv-tests, and anything the core does not implement (interrupts, privilege modes, unaligned access).