How it works

TinyCPU is a 32-bit RISC-V (RV32I) processor written in SystemVerilog. It has two cores that share one instruction set: a single-cycle reference core, which finishes one instruction per clock, and a 5-stage pipelined core, which overlaps instructions and handles the hazards that creates.

Everything on this site runs the real hardware. The SystemVerilog is compiled by Verilator into C++, the C++ is compiled by Emscripten into WebAssembly, and the browser steps that WebAssembly one clock edge at a time. Nothing is simulated in JavaScript.

The chain, from source to screen

• RTL: rtl/*.sv, both cores and the memory-mapped I/O.
• Verilator: turns the RTL into one C++ model per core, so both run in one WebAssembly module.
• Emscripten: links the models into tiny_cpu.wasm, about 77 KB gzipped.
• The app: an assembler and a viewer that show every cycle, every register and every byte of memory.

Try it: a program on the single-cycle core

The program below prints a greeting one byte at a time through the console register, then reports PASS. On the single-cycle core every instruction takes exactly one cycle, so the cycle count equals the instruction count. Step through it.

Where to go next

• Architecture: the memory map, the two cores and how they are checked.
• The pipeline: the five stages, and what happens to an instruction in each.
• Hazards: when the pipeline has to wait, and how forwarding avoids it.
• Verification: what is tested, and against what.