A real RISC-V CPU, running in your browser.
TinyCPU is a 32-bit RISC-V processor written in SystemVerilog, with a single-cycle core and a 5-stage pipeline. The hardware is compiled to WebAssembly, so the clock you see below is the real design, stepping one cycle at a time.
Fibonacci on the pipeline
This runs live in your browser. Step through it to watch five instructions share the pipeline.
Loading the core…
Two cores
A single-cycle reference and a 5-stage pipeline with forwarding, stalls and branch flushes.
Checked, not assumed
40 official RISC-V tests and 260 random programs agree with a golden model, and pipeline cycle counts match an independent timing model.
Every cycle visible
Registers, memory, hazards and the datapath, one clock edge at a time.