The pipeline
The pipelined core works on five instructions at once, one per stage. A new instruction starts every cycle, so in steady state the core finishes one instruction per cycle, as the single-cycle core does, when no hazard interrupts the flow.
The five stages
| Stage | What happens |
|---|---|
| IF | Fetch the instruction at the program counter. |
| ID | Decode it and read the source registers. |
| EX | Compute the ALU result, or the branch decision, or a memory address. |
| MEM | Load from or store to data memory. |
| WB | Write the result to the destination register. |
Watch it run
This is the Fibonacci program on the pipelined core, with forwarding on. The stage boxes show which instruction is in each stage on the selected cycle. Step through a few cycles and watch the first instructions move through the stages.
Loading the core…
Two things that break the flow
- A hazard is an instruction that needs a value the pipeline has not produced yet. The pipeline either forwards the value from a later stage or stalls. See Hazards.
- A taken branch changes the program counter after two instructions have already been fetched behind it. The pipeline predicts that branches are not taken, and when one is taken it discards those two instructions.